Sequential Logic: Latches, Flip-Flops, Shift Registers, and Counters (EGR 2440 Module 4 Study Guide)

Sequential Logic Overview

Introduction

Sequential logic circuits are fundamental building blocks in digital systems, storing and manipulating data based on clock signals. Unlike combinational logic, sequential logic depends on both current inputs and previous states, enabling memory and timing control in digital devices.

• Synchronous logic: All elements change state in response to a common clock signal.

• Asynchronous logic: Elements change state immediately in response to input changes, without a clock.

Latches

SR Latch (Set-Reset Latch)

An SR latch is a basic storage element constructed from NOR or NAND gates. It has two inputs: Set (S) and Reset (R), and two outputs: Q and Q' (complementary).

• Set (S = 1, R = 0): Q = 1 (Set state)

• Reset (S = 0, R = 1): Q = 0 (Reset state)

• Memory (S = 0, R = 0): Q holds previous value

• Invalid (S = 1, R = 1): Not allowed (forbidden state)

Characteristic: Level-sensitive; responds immediately to input changes while enabled.

SR Latch with Enable

This variant adds an enable (EN) input, allowing the latch to respond to S and R only when enabled.

• EN = 0: Latch disabled, Q holds previous state

• EN = 1: Latch enabled, responds to S and R

• Same input combinations as basic SR latch apply

D Latch

The D latch removes the invalid state by ensuring S and R are never 1 simultaneously. It has a single data input (D) and an enable input (EN).

• EN = 1: Q follows D

• EN = 0: Q holds previous value

Flip-Flops

D Flip-Flop

A D flip-flop stores bits precisely at clock edges, using two D latches in a master-slave configuration. It is edge-triggered, meaning data is stored only on a clock transition (usually rising edge).

• Clock = 0: First latch stores input value

• Clock rising edge: Second latch stores value from first latch

• Output remains constant until next clock edge

Practical D Flip-Flop (FPGA Implementation)

In FPGAs, the basic register primitive is a D-type flip-flop with built-in clock enable and usually reset/set. Synthesis tools infer DFF + Clock Enable by default when HDL implies enable.

• Do not make preset (PRN) or clear (CLRN) active at start

• Clock enable is used for conditional data storage

Setup and Hold Times

Setup and hold times are critical for reliable operation of flip-flops:

• Setup time ($t_{setup}$): Minimum time before the clock edge that the D input must be stable

• Hold time ($t_{hold}$): Minimum time after the clock edge that the D input must remain stable

• If violated, flip-flop may capture incorrect value or become metastable

D Flip-Flop in VHDL

VHDL code for a D flip-flop typically includes asynchronous controls (preset/clear), clock enable, and data input/output.

architecture behavioral of dffe_vhdl is signal q_reg : std_logic := '0'; begin process(clk, prn, clrn) begin -- Asynchronous controls (active low preset) if clrn = '0' then q_reg <= '0'; elsif prn = '0' then q_reg <= '1'; elsif rising_edge(clk) then if en = '1' then q_reg <= d; -- load on enable end if; -- else hold end if; end process; q <= q_reg; end architecture behavioral;

Shift Registers

Introduction

Shift registers are sequential circuits that store and move data in a specific direction (left or right) through a series of flip-flops. They are used for temporary data storage, data transfer, and serial/parallel data conversion.

Types of Shift Registers

Type	Input	Output	Application
SISO	Serial	Serial	Delay line, temporary buffer
SIPO	Serial	Parallel	Serial-to-parallel conversion
PISO	Parallel	Serial	Parallel-to-serial conversion
PIPO	Parallel	Parallel	Temporary storage, fast transfer

SISO (Serial-In Serial-Out) Shift Register

• Data is shifted in and out serially, one bit at a time

• Consists of flip-flops connected in series

• Each bit shift occurs on clock edge

SIPO (Serial-In Parallel-Out) Shift Register

• Data is shifted in serially, output is available in parallel

• Used for serial-to-parallel data conversion

• Common in communication systems

PISO (Parallel-In Serial-Out) Shift Register

• Data is loaded in parallel, shifted out serially

• Used for parallel-to-serial data conversion

• Reduces number of transmission lines

PIPO (Parallel-In Parallel-Out) Shift Register

• Data is loaded and read in parallel

• Used for temporary storage and fast data transfer

Counters

Introduction

Counters are sequential digital circuits that count the number of input signals, usually clock pulses. They are widely used for event counting, frequency division, and state tracking.

Types of Counters

Type	Triggering	Direction	Application
Synchronous	All flip-flops triggered by clock	Up/Down	Reliable, easy timing analysis
Asynchronous (Ripple)	Flip-flops triggered by previous stage	Up/Down	Simple, but timing issues

Counter Operation

• Up Counter: Increments count on each clock pulse

• Down Counter: Decrements count on each clock pulse

• Up/Down Counter: Can count both up and down based on control signal

• Modulus (Mod-N): Number of unique states before resetting (e.g., Mod-8 counter counts 0 to 7)

Counter Design Signals

• clk: Drives sequential behavior

• rst_n: Asynchronous or synchronous reset

• en: Enable signal for counting

• count: Output value of the counter

Synchronous Design Rules

Best Practices

• Use one clock per block

• Always use rising_edge(clk) for state changes

• Do not gate the clock in logic; use clock enable instead

• Use dedicated clock resources

• Assert asynchronous reset, deassert synchronously

• Avoid combinational loops and long feedback paths

• Keep critical path short; add pipeline registers if timing is tight

Frequency Division

Introduction

Frequency dividers generate lower-frequency signals from a high-frequency clock, enabling systems to operate at different speeds.

• Commonly implemented using counters

• Example: Divide 50 MHz clock to 5 MHz using a counter

Example VHDL Code for Frequency Divider

process(clk) begin if rising_edge(clk) then if cnt = 9 then cnt <= 0; out <= not out; else cnt <= cnt + 1; end if; end if; end process;

Summary Table: Sequential Logic Elements

Element	Inputs	Outputs	Characteristic
SR Latch	S, R	Q, Q'	Level-sensitive, memory, forbidden state
D Latch	D, EN	Q	Level-sensitive, no forbidden state
D Flip-Flop	D, CLK	Q	Edge-triggered, synchronous
Shift Register	Serial/Parallel, CLK	Serial/Parallel	Data movement, storage
Counter	CLK, EN, RST	Count	Event counting, frequency division

Additional info:

• JK and T flip-flops are also used in counter design for their toggling behavior.

• Recovery and removal times are advanced timing parameters relevant for setup/hold analysis.

• VHDL (VHSIC Hardware Description Language) is used to model and simulate sequential logic circuits.