Question 1

Which of the following statements best describes the difference between synchronous and asynchronous sequential logic circuits?

Accepted Answer

Synchronous circuits change state only at specific clock edges, while asynchronous circuits can change state at any time based on input changes.

Question 2

In a basic SR latch built from NOR gates, what happens if both S and R inputs are set to 1 simultaneously?

Accepted Answer

The output Q enters an invalid or undefined state.

Question 3

A D flip-flop is used in a digital system to store a bit. If the setup time $$t_{setup} is $$violated, which of the following is the most likely outcome?

Accepted Answer

The flip-flop may capture an incorrect value or become metastable.

Question 4

Which type of shift register would you use to convert serial data from a sensor into parallel data for a microcontroller?

Accepted Answer

Serial-in Parallel-out (SIPO) shift register

Question 5

A 4-bit synchronous counter is designed to count from 0 to 15. What is the modulus (MOD) of this counter?

Accepted Answer

$$16$$

Question 6

In VHDL, which signal is typically used to ensure that a flip-flop only changes state on the rising edge of the clock?

Accepted Answer

$$rising\_edge(clk)$$

Question 7

A frequency divider circuit receives a $$50\ \mathrm{MHz}$$ clock and outputs a $$5\ \mathrm{MHz}$$ signal. What is the division factor?

Accepted Answer

$$10$$

Question 8

Which of the following is a key advantage of synchronous design in digital systems?

Accepted Answer

Deterministic timing and easier analysis due to state changes only on clock edges.

Question 9

A JK flip-flop is used in a counter circuit. What happens when both J and K inputs are high at the clock edge?

Accepted Answer

The output Q toggles its state.

Question 10

In a digital system, a shift register is used as a delay line. If the clock period is $$20\ \mathrm{ns}$$ and the register is 4 bits long, what is the total delay introduced?

Accepted Answer

$$80\ \mathrm{ns}$$

Question 11

Which of the following VHDL code fragments correctly implements an asynchronous clear for a D flip-flop?

Accepted Answer

if clrn = '0' then q_reg \u003c= '0';

Question 12

A parallel-in serial-out (PISO) shift register is used to transmit 8 bits of data over a single line. How many clock cycles are required to transmit all bits?

Accepted Answer

$$8$$

Question 13

What is the primary function of the enable (EN) input in a latch or flip-flop circuit?

Accepted Answer

It allows the storage element to respond to input changes only when EN is active.

Question 14

A 4-bit up/down counter is set to count up when the control signal is high. If the current state is $$0110_2$$ and a clock pulse occurs, what is the next state?

Accepted Answer

$$0111_2$$

Question 15

Which of the following is a potential issue if both setup and hold times are violated in a flip-flop?

Accepted Answer

The flip-flop may enter a metastable state.

Question 16

In a synchronous counter, what is the role of the ripple carry out (RCO) signal?

Accepted Answer

It indicates when the counter has reached its maximum value and will wrap around.

Question 17

Which of the following is NOT a recommended synchronous design rule for digital systems?

Accepted Answer

Use combinational loops for feedback paths.

Question 18

A register is used to temporarily store data in a digital system. Which component is typically used to build a register?

Accepted Answer

Flip-flops

Question 19

In a real-world application, why might a PISO shift register be used to transmit data between a microcontroller and a peripheral device?

Accepted Answer

To reduce the number of data lines required for transmission.

Question 20

A digital system uses a SISO shift register as a delay line. If the input data rate is $$1\ \mathrm{Mbps}$$ and the register is 8 bits long, what is the delay in microseconds?

Accepted Answer

$$8\ \mu s$$

Sequential Logic: Latches, Flip-Flops, Shift Registers, and Counters (EGR 2440 Module 4 Study Guide)

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