50% off Pearson+ for summer. Check it out

Modern VLSI Design: System-on-Chip Design, 3rd edition

  • Wayne Wolf

Unfortunately, this item is not available in your country.

Overview

A new edition of this title is available, ISBN-10: 0137145004 ISBN-13: 9780137145003

 

For Electrical Engineering and Computer Engineering courses that cover the design and technology of very large scale integrated (VLSI) circuits and systems. May also be used as a VLSI reference for professional VLSI design engineers, VLSI design managers, and VLSI CAD engineers.

Modern VSLI Design provides a comprehensive “bottom-up” guide to the design of VSLI systems, from the physical design of circuits through system architecture with focus on the latest solution for system-on-chip (SOC) design. Because VSLI system designers face a variety of challenges that include high performance, interconnect delays, low power, low cost, and fast design turnaround time, successful designers must understand the entire design process. The Third Edition also provides a much more thorough discussion of hardware description languages, with introduction to both Verilog and VHDL. For that reason, this book presents the entire VSLI design process in a single volume.

Table of contents



Preface to the Third Edition.


Preface to the Second Edition.


Preface.


1. Digital Systems and VLSI.

Why Design Integrated Circuits? Integrated Circuit Manufacturing. CMOS Technology. Integrated Circuit Design Techniques. A Look into the Future. Summary. References. Problems.



2. Transistors and Layout.

Introduction. Fabrication Processes. Transistors. Wires and Vias. Design Rules. Layout Design and Tools. References. Problems.



3. Logic Gates.

Introduction. Combinational Logic Functions. Static Complementary Gates. Switch Logic. Alternative Gate Circuits. Low-Power Gates. Delay Through Resistive Interconnect. Delay Through Inductive Interconnect. References. Problems.



4. Combinational Logic Networks.

Introduction. Standard Cell-Based Layout. Simulation. Combinational Network Delay. Logic and Interconnect Design. Power Optimization. Switch Logic Networks. Combinational Logic Testing. References. Problems.



5. Sequential Machines.

Introduction. Latches and Flip-Flops. Sequential Systems and Clocking Disciplines. Sequential System Design. Power Optimization. Design Validation. Sequential Testing. References. Problems.



6. Subsystem Design.

Introduction. Subsystem Design Principles. Combinational Shifters. Adders. ALUs. Multipliers. High-Density Memory. Field-Programmable Gate Arrays. Programmable Logic Arrays. References. Problems.



7. Floorplanning.

Introduction. Floorplanning Methods. Off-Chip Connections. References. Problems.



8. Architecture Design.

Introduction. Hardware Description Languages. Register-Transfer Design. High-Level Synthesis. Architectures for Low Power. Systems-on-Chips and Embedded CPUs. Architecture Testing. References. Problems.



9. Chip Design.

Introduction. Design Methodologies. Kitchen Timer Chip. Microprocessor Data Path. References. Problems.



10. CAD Systems and Algorithms.

Introduction. CAD Systems. Switch-Level Simulation. Layout Synthesis. Layout Analysis. Timing Analysis and Optimization. Logic Synthesis. Test Generation. Sequential Machine Optimizations. Scheduling and Binding. Hardware/Software Co-Design. References. Problems.



Appendix A: A Chip Designer's Lexicon.


Appendix B: Chip Design Projects.

Class Project Ideas. Project Proposal and Specification. Design Plan. Design Checkpoints and Documentation.



Appendix C: Kitchen Timer Model.

Hardware Modeling in C.



Index.

Published by Pearson (January 14th 2002) - Copyright © 2002