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Topic I. Overview of VLSI Design Methodology
2. VLSI Design Methodology
3. Hierarchical Design Decomposition
Topic II. Modeling
Topic III. Design Validation
5. Characteristics of Functional Validation
6. Characteristics of Formal Equivalency Verification
Topic IV. Design Implementation
7. Logic Synthesis
Topic V. Electrical Analysis
10. Layout Parasitic Extraction and Electrical Modeling
11. Timing Analysis Section
12. Noise Analysis
13. Power Analysis
14. Power Rail Voltage Drop Analysis
15. Electromigration (EM) Reliability Analysis
16. Miscellaneous Electrical Analysis Requirements
Topic VI. Preparation for Manufacturing Release and Bring-up
18. Physical Design Verification
19. Design-for-Testability Analysis
20. Preparation for Tapeout
21. Post-Silicon Debug and Characterization (Bring-up) and Product Qualification
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has more than 30 years of experience in the microelectronics industry, including semiconductor circuit design, fabrication process research, and EDA tool development. He has been responsible for the design methodology development for ASIC, SoC, and complex microprocessor chips for IBM, Sun Microsystems/Oracle, and AMD. He is the author of the book VLSI Engineeri
ng and has written for SemiWiki.
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