VHDL for Engineers, Pearson New International Edition, 1st edition

Published by Pearson (1 November 2013) © 2014

  • Kenneth L. Short University of New York-Stony Brook
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  • A print edition

Title overview

Suitable for use in a one- or two-semester course for computer and electrical engineering majors.

VHDL for Engineers teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.

Table of contents

Preface

1 Digital Design Using VHDL and PLDs 1

1.1 VHDL/PLD Design Methodology 1

1.2 Requirements Analysis and Specification 5

1.3 VHDL Design Description 6

1.4 Verification Using Simulation 11

1.5 Testbenches 13

1.6 Functional (Behavioral) Simulation 16

1.7 Programmable Logic Devices (PLDs) 18

1.8 SPLDs and the 22V10 21

1.9 Logic Synthesis for the Target PLD 27

1.10 Place-and-Route and Timing Simulation 31

1.11 Programming and Verifying a Target PLD 37

1.12 VHDL/PLD Design Methodology Advantages 38

1.13 VHDL’s Development 39

1.14 VHDL for Synthesis versus VHDL for Simulation 39

1.15 This Book’s Primary Objective 40

 

2 Entities , Architectures , and Coding Styles 44

2.1 Design Units, Library Units, and Design Entities 44

2.2 Entity Declaration 45

2.3 VHDL Syntax Definitions 47

2.4 Port Modes 50

2.5 Architecture Body 53

2.6 Coding Styles 55

2.7 Synthesis Results versus Coding Style 66

2.8 Levels of Abstraction and Synthesis 69

2.9 Design Hierarchy and Structural Style 71

 

3 Signals and Data Types 82

3.1 Object Classes and Object Types 82

3.2 Signal Objects 84

3.3 Scalar Types 88

3.4 Type Std_Logic 93

3.5 Scalar Literals and Scalar Constants 99

3.6 Composite Types 100

3.7 Arrays 101

3.8 Types Unsigned and Signed 107

3.9 Composite Literals and Composite Constants 110

3.10 Integer Types 112

3.11 Port Types for Synthesis 116

3.12 Operators and Expressions 118

 

4 Dataf low Style Combinational Design 123

4.1 Logical Operators 123

4.2 Signal Assignments in Dataflow Style Architectures 127

4.3 Selected Signal Assignment 130

4.4 Type Boolean and the Relational Operators 132

4.5 Conditional Signal Assignment 134

4.6 Priority Encoders 139

4.7 Don’t Care Inputs and Outputs 140

4.8 Decoders 144

4.9 Table Lookup 147

4.10 Three-state Buffers 151

4.11 Avoiding Combinational Loops 155

 

5 Behavi oral Style Combinational Design 165

5.1 Behavioral Style Architecture 165

5.2 Process Statement 169

5.3 Sequential Statements 170

5.4 Case Statement 171

5.5 If Statement 176

5.6 Loop Statement 181

5.7 Variables 185

5.8 Parity Detector Example 188

5.9 Synthesis of Processes Describing Combinational Systems 193

 

6 Event-Driven Simulation 201

6.1 Simulator Approaches 201

6.2 Elaboration 203

6.3

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